The Scalable CMOS (SC) rules support both n-well and p-well processes. MOSIS recognizes three base technology codes that let the designer specify the well type of the process selected. SCN specifies an n-well process, SCP specifies a p-well process, and SCE indicates that the designer is willing to utilize a process of either n-well or p-well.
An SCE design must provide both a drawn n-well and a drawn p-well; MOSIS will use the well that corresponds to the selected process and ignore the other well. As a convenience, SCN and SCP designs may also include the other well (p-well in an SCN design or n-well in an SCP design), but it will always be ignored.
MOSIS currently offers only n-well processes or foundry-designated twin-well processes that from the design and process flow standpoints are equivalent to n-well processes. These twin-well processes may have options (deep n-well) that provide independently isolated p-wells. For all of these processes at this time use the technology code SCN. SCP is currently not supported, and SCE is treated exactly as SCN.
Designation | Long Form | Description |
E | Electrode | Adds a second polysilicon layer (poly2) that can serve either as the upper electrode of a poly capacitor or (1.5 micron only) as a gate for transistors |
A | Analog | Adds electrode (as in E option), plus layers for vertical NPN transistor pbase |
3M | 3 Metal | Adds second via (via2) and third metal (metal3) layers |
4M | 4 Metal | Adds 3M plus third via (via3) and fourth metal (metal4) layers |
5M | 5 Metal | Adds 4M plus fourth via (via4) and fifth metal (metal5) layers |
6M | 6 Metal | Adds 5M plus fifth via (via5) and sixth metal (metal6) layers |
LC | Linear Capacitor | Adds a cap_well layer for linear capacitors |
PC | Poly Cap | Adds poly_cap, a different layer for linear capacitors |
SUBM | Sub-Micron | Uses revised layout rules for better fit to sub-micron processes (see section 2.4) |
DEEP | Deep | Uses revised layout rules for better fit to deep sub-micron processes (see section 2.4) |
Foundry | Process | Lambda (micrometers) | Options |
AMI | ABN (1.5 micron n-well) | 0.80 | SCNA, SCNE |
AMI | C5N (0.5 micron n-well) | 0.35 | SCN3M, SCN3ME |
Agilent/HP | AMOS14TB (0.5 micron n-well) | 0.35 | SCN3M, SCN3MLC |
TSMC | 0.35 micron 2P4M (4 Metal Polycided, 3.3 V/5 V) | 0.25 | SCN4ME |
TSMC | 0.35 micron 1P4M (4 Metal Silicided, 3.3 V/5 V) | 0.25 | SCN4M |
Foundry | Process | Lambda (micrometers) | Options |
AMI | C5N (0.5 micron n-well) | 0.30 | SCN3M_SUBM, SCN3ME_SUBM |
Agilent/HP | AMOS14TB (0.5 micron n-well) | 0.30 | SCN3M_SUBM, SCN3MLC_SUBM |
TSMC | 0.35 micron 2P4M (4 Metal Polycided, 3.3 V/5 V) | 0.20 | SCN4ME_SUBM |
TSMC | 0.35 micron 1P4M (4 Metal Silicided, 3.3 V/5 V) | 0.20 | SCN4M_SUBM |
TSMC | 0.25 micron 5 Metal 1 Poly (2.5 V/3.3 V) | 0.15 | SCN5M_SUBM |
TSMC | 0.18 micron 6 Metal 1 Poly (1.8 V/3.3 V) | 0.10 | SCN6M_SUBM |
Foundry | Process | Lambda (micrometers) | Options |
TSMC | 0.25 micron 5 Metal 1 Poly (2.5 V/3.3 V) | 0.12 | SCN5M_DEEP |
TSMC | 0.18 micron 6 Metal 1 Poly (1.8 V/3.3 V) | 0.09 | SCN6M_DEEP |
Rule |
Description |
SCMOS |
SCMOS sub-micron |
1.1, 17.1 | Well width | 10 | 12 |
1.2, 17.2 | Well space (different potential) |
9 | 18 |
2.3 | Well overlap (space) to transistor |
5 | 6 |
3.2 | Poly space | 2 | 3 |
5.3, 6.3 | Contact space | 2 | 3 |
5.5b | Contact to Poly space to Poly |
4 | 5 |
7.2 | Metal1 space | 2 | 3 |
7.4 | Minimum space (when metal line is wider than 10 lambda) |
4 | 6 |
8.5 | Via on flat | 2 | Unrestricted |
11.1 | Poly2 width | 3 | 7 |
11.3 | Poly2 overlap | 2 | 5 |
11.5 | Space to Poly2 contact | 3 | 6 |
13.2 | Poly2 contact space | 2 | 3 |
15.1 | Metal3 width (3 metal process only) |
6 | 5 |
15.2 | Metal3 space (3 metal process only) |
4 | 3 |
15.4 | Minimum space (when metal line is wider than 10 lambda) (3 metal process only) |
8 | 6 |
17.3 | Minimum spacing to external Active | 5 | 6 |
17.4 | Minimum overlap of Active | 5 | 6 |
Rule |
Description |
SCMOS sub-micron |
SCMOS DEEP |
3.2 | Poly space over field |
3 | 3 |
3.2.a | Poly space over Active |
4 | |
3.3 | Minimum gate extension of Active |
2 | 2.5 |
3.4 | Active extension beyond Poly |
3 | 4 |
4.3 | Select overlap of Contact |
1 | 1.5 |
4.4 | Select width and
space (p+ to p+ or n+ to n+) |
2 | 4 |
5.3, 6.3 | Contact spacing | 3 | 4 |
8.1 | Via width | 2 | 3 |
9.2 | Metal2 space | 3 | 4 |
9.4 | Minimum space (when metal line is wider than 10 lambda) |
6 | 8 |
14.1 | Via2 width | 2 | 3 |
15.2 | Metal3 space | 3 | 4 |
15.4 | Minimum space (when metal line is wider than 10 lambda) (for 4+ metal processes) |
6 | 8 |
21.1 | Via3 width | 2 | 3 |
22.2 | Metal4 space (for 5+ metal processes) |
3 | 4 |
22.4 | Minimum space (when metal line is wider than 10 lambda) |
6 | 8 |
25.1 | Exact size | 2 x 2 | 3 x 3 |
26.2 | Metal5 space | 3 | 4 |
26.3 | Minimum overlap
of Via4 (for 5 metal process only) |
1 | 2 |
26.4 | Via4 overlap | 6 | 8 |
29.1 | Exact size | 3 x 3 | 4 x 4 |
30.3 | Minimum overlap of Via5 | 1 | 2 |
Technology code with link to layer map |
Process | Stacked vias |
---|---|---|
SCNE | AMI 1.50 (ABN) | No |
SCNA | AMI 1.50 (ABN) | No |
SCNPC | AMI 0.80 (CWL) | No |
SCN3M |
Agilent/HP 0.50 (AMOS14TB) |
No |
AMI 0.50 (C5N) | Yes | |
SCN3ME | AMI 0.50 (C5N) | Yes |
SCN3MLC |
Agilent/HP 0.50 (AMOS14TB) |
No |
SCN4M |
Agilent/HP 0.35 (GMOS10QA), TSMC 0.35 |
Yes |
SCN4ME | TSMC 0.35 | Yes |
SCN5M | TSMC 0.25 | Yes |
SCN6M | TSMC 0.18 | Yes |