MOSIS Layer Map for SCNE and SCNA

This is the layer map for the technology codes SCNA and SCNE using the MOSIS Scalable CMOS layout rules (SCMOS), and only for SCNA and SCNE. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCNE: Two metal, two poly. Second polysilicon layer (poly2) can serve either as the upper electrode of poly capacitor or as a gate for transistors.

SCNA: Same as SCNE, adds layers for vertical NPN transitor pbase.

Fabricated on AMI 1.50 micron process runs.