MOSIS Layer Map for SCN5M_SUBM and SCN5M_DEEP

This is the layer map for the technology codes SCN5M_SUBM and SCN5M_DEEP using the MOSIS Scalable CMOS layout rules ( SCMOS), and only for SCN5M_SUBM and SCN5M_DEEP. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCN5M_SUBM: Scalable CMOS N-well, 5 metal, 1 poly, thick oxide option, and supports silicide block. MiM (Cap_Top_Metal, also known as Metal 4 Prime, to Metal 4) capacitors are available. Uses revised layout rules for better fit to sub-micron processes (see section 2.4)

SCN5M_DEEP: Uses revised layout rules for better fit to deep sub-micron processes (see section 2.4)

Fabricated on TSMC 0.25 micron process runs.