MOSIS Layer Map for SCN3MLC and SCN3MLC_SUBM

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This is the layer map for the technology code SCN3MLC and SCN3MLC_SUBM using the MOSIS Scalable CMOS layout rules ( SCMOS), and only for SCN3MLC and SCN3MLC_SUBM. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCN3MLC: Scalable CMOS N-well, 3 metal, 1 poly, silicide block option, adds a cap_well layer for linear capacitors.

SCN3MLC_SUBM: Uses revised layout rules for better fit to sub-micron processes (see section 2.4). Adds a cap_well layer for linear capacitors.

Fabricated on Agilent/HP 0.50 micron process runs.


Layer GDS CIF CIF Synonym Rule
Section
Notes
N_WELL 42 CWN   1  
CAP_WELL 59 CWC   17, 18 Optional
ACTIVE 43 CAA   2
POLY 46 CPG   3
SILICIDE_BLOCK 29 CSB   20 Optional
N_PLUS_SELECT 45 CSN   4
P_PLUS_SELECT 44 CSP   4
CONTACT 25 CCC CCG 5, 6  
POLY_CONTACT 47 CCP   5 Can be replaced by CONTACT
ACTIVE_CONTACT 48 CCA   6 Can be replaced by CONTACT
METAL1 49 CM1 CMF 7
VIA 50 CV1 CVA 8
METAL2 51 CM2 CMS 9
VIA2 61 CV2 CVS 14  
METAL3 62 CM3 CMT 15  
GLASS 52 COG   10
PADS 26 XP  
Non-fab layer used to highlight pads
Comments -- CX     Comments