ECE 124d / ECE 256c
Forrest Brewer (729-1410) forrest@ece.ucsb.edu
TA: Merritt Miller merritt@irq9.com
TA Section:Wed 2-3pm TBA (section attendance is required)
Text: "Digital Systems Engineering", Dally and Poulton (a solid reference, but dated)
Ref1: "High Speed CMOS Design Styles", Bernstein et. al., Kluwer
Academic Publishers
Ref2: "Signal and Power Integrity- SIMPLIFIED", Bogatin, Prentice-Hall
Meeting Times: 10-11 MWF Phelps 3515
Announcements:
Note -- on the power lab -- ignore the startup transients -- i.e. wait until the power stabilizes --
up to 1mS before doing the power simulation. On practical systems there is a power-good signal that allows
this behavior.
Notes on Lab Write-ups
Notes:
Textbook Errata
PBS
Lecture Foils:
Note: Lectures will be updated periodically
Lecture1 PDF
Lecture2 PDF
Lecture3 PDF
Lecture4 PDF
Lecture5 PDF
Lecture6 PDF
Transmission Line/ On-chip Noise Notes (lec
1 ref)
Elmore's original paper (lecture 3 ref* interest only)
Elmore delay in a tree (Penfield) (lecture 3 ref)
Bakoglu's Optimal Interconnect (lecture 3 ref)
Power/Ground Issues in Buffers (lecture 3/5 ref)
Intel 45nm Process Overview
CPL_Multiplier (lec 4 ref)
Flip-flop_Optimization (lec 4 ref)
On-Chip Power Distribution (lec 5 ref)
On-Chip Inherent Power Decoupling (lec 5
ref)
Low Inductance Capacitors (lec 5 ref)
Multiple Size Capacitor Decoupling
(lec 5 ref)
Intro to Decoupling with Capacitors (lec 5 ref)
Design of Large Processor Clock/Power/System
(lec 5/6 ref)
Clock-distribution TM lines (lec 6 ref)
Setup files and instructions Labs are
often updated -- Contact me if you wish to start a lab early.
Lab1
Lab1b
Lab 2
Lab3
Lab4
Lab5
Final_Lab
Monte Carlo instructions
Quiz: