Text: "Digital Systems Engineering", Dally and Poulton
Ref1: "High Speed CMOS Design Styles", Bernstein et. al., Kluwer Academic Publishers
Ref2: "Modeling, Synthesis and Rapid Prototyping with the Verilog HDL" (2nd edition), Ciletti (Prentice Hall)

Meeting Times: 10-11 MWF ESB 1003, ECI Lab

Announcements:

Notes: 
Textbook Errata
Elmore's original paper
Elmore delay in a tree
Bakoglu's Optimal Interconnect
CPL_Multiplier
Flip-flop_Optimization
PBS 
Power_Ground Buffer Analysis
Transmission Line/ On-chip Noise Notes
Low Inductance Capacitors
Multiple Size Capacitor Decoupling
Intro to Decoupling with Capacitors
On-Chip Power Distribution
On-Chip Inherent Power Decoupling
Design of Large Processor Clock/Power/System
Clock-distribution TM lines

Lecture Foils:
Note: Lectures will be updated periodically during class
Lecture1 ppt ps
Lecture2 ppt ps
Lecture3 ppt ps
Lecture4 ppt ps
Lecture5 ppt ps
Lecture6 ppt ps

Homework: (Will be updated during quarter)
Note: The soultions posted are for older homework versions; New soultions will be posed soon
Homework 1      Soultion    More soultions
Homework 2      Soultion    More soultions
Homework 3      Soultion
Homework 4
Homework 5
Homework 6
Homework 7

Labs: Setup files and instructions
Monte Carlo instructions
Lab1(pdf)
Lab2(pdf)
Lab3(pdf)
Lab4 (pdf)
Lab5(pdf)
Lab6(pdf)
Final Lab(pdf)

These labs are for referece only -- new ones will be posted during the quarter.
Lab2a 
Lab2b 
Lab3a 
Lab3b 
Lab4