UCSB

Prof. Brewer's Research Site

University of California, Santa Barbara


Research

Low Power Feedback Control:
  • Algorithm/Metrics
  • Processors
  • Signal Processing
Latency Tolerant Synthesis/Design:
  • PyTDL Language
  • SELF Synthesis
  • Pilot Designs
Pulse-Mode On-Chip Signalling

CAD Symmetry Exploitation:
XPIC

Publications

(Updates in Progress)

Calendar

(Lab Members Only)

Classes

ENGR5a
ECE 124a
ECE 124d/ECE 256c
ECE256bd
ECE 224a
ECE 224b
ECE 253/ECE 153a

Support

We gratefully acknowledge the support of the following organizations:

Atrenta Corporation
INTEL Corporation
Ricoh Corporation
Chameleon Corporation
National Science Foundation
Semiconductor Research Corporation

Downloads

  • PyTDL: Distributed Latency Tolerant Verilog Compiler (v.1.0) SRC/Intel/NSF
  • PYABSS: Python implementation of Automata-Based Symbolic Scheduling
  • PyCUDD: Python Interface to the CUDD BDD Package

[ High Level Synthesis | CAD | Test | ECE Department | College of Engineering | UCSB ]
Website comments/questions/problems: chsegal at ece dot ucsb dot edu