Symbolic Data Path Modeling

Chuck Monahan Forrest Brewer


Our research is concentrated on the representation of a data path. Specifically, we are interested how new problems, in the form of a data-flow graph (DFG), can be cast upon on existing data-path design.

Why? This work is based on the notion that an application whose performance is optimized for an existing system can be a superior product than one which incorporates a specialized chip design or application specific IC (ASIC). Time-to-market, upgradability, design cost, and production cost are examples of factors which affect this decision.

There are many problems involved when mapping a problem to an existing architecture. Our research shares many of the goals of compilers which schedule and assign (bind) operands to specific memory locations and operations to specific components. While these scheduling and binding problems are familiar to the field of High Level Synthesis, the introduction of the data-path designs causes new complications. Traditionally, High Level Synthesis has dealt with the creation of ASIC's where the data path is tailored to the behavior of problem. These techniques focus on creating the data-path around the application. Alternatively, we must consider the mapping of the application to the constraints of the data path.

The following data-path issues are ones that we have incorporated into our model.


"Symbolic Data Path Analysis", Ph.D. thesis

"Scheduling and Binding Bounds for RT-Level Symbolic Execution", Int. Conf. Computer Aided Design, 1997.

"Concurrent Analysis Techniques for Data Path Timing Optimization", Design Automation Conf., 1996.

"Symbolic Modeling and Evaluation of Data Paths", Design Automation Conf., 1995.

"Symbolic Execution of Data Paths", Proc. of 5th Great Lakes Symp. on VLSI. Also available in postscript.

"Communication Driven Interconnection Synthesis", Proc. of 6th International Workshop on High Level Synthesis.