Why? This work is based on the notion that an application whose performance is optimized for an existing system can be a superior product than one which incorporates a specialized chip design or application specific IC (ASIC). Time-to-market, upgradability, design cost, and production cost are examples of factors which affect this decision.
There are many problems involved when mapping a problem to an existing architecture. Our research shares many of the goals of compilers which schedule and assign (bind) operands to specific memory locations and operations to specific components. While these scheduling and binding problems are familiar to the field of High Level Synthesis, the introduction of the data-path designs causes new complications. Traditionally, High Level Synthesis has dealt with the creation of ASIC's where the data path is tailored to the behavior of problem. These techniques focus on creating the data-path around the application. Alternatively, we must consider the mapping of the application to the constraints of the data path.
The following data-path issues are ones that we have incorporated into our model.
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