University of California,
Department of Electrical and Computer Engineering
VLSI Project Design
ECE 224A - Spring 2011
Instructor: Prof. Forrest Brewer 729-1410
Schedule:Mon/Wed 10-12 Phelps 1431
The course curricula and tools now support mixed signal design practice as well as conventional digial design. Projects may be either digital, mixed or analog as desired. The tools will include Cadence Virtuoso and Silicon Encounter as well as Synopsys Design Compiler for Verilog based design. We will also support full custom, array and data path tools from MMI. All designs will use the On-Semi 0.6um C5 process through the MOSIS SCMOS rules which implement a 3-metal, 2-poly technology that can accommodate standard cell digital designs as large as 2k gates in the default size (1.5 sq. mm). It supports high quality capacitor, resistor, and NPN-bipolar transistors in addition to thin and thick oxide complementary FET’s. Since the design area is relatively small for this level of integration, projects will have limited external signalling capacity, and are encouraged to integrate sensors such as photo-diodes, Hall-effect devices, or mixed-signal designs in lieu of pure digital constructions.
There is a portable linux version of the MMI tool set available for personal computer use in this course so that design and analysis work need not be completed in the ECI lab. If interested, please see me about this.
Sample Project Report
This course stresses practical layout and
full/semi-custom design techniques leading to fabrication of VLSI
integrated circuits. Given the short design time, a structured
methodology will be used stressing design modeling and constraint based
design. The projects will be completed by small groups (2-4 people) and must meet design goals including area, performance,
validation, test and manufacturability to complete the course. These
constraints ensure that the final design can be fabricated and that
every measure has been taken to ensure a working design.
Course Organization: Lectures M,W 10-12, periodic homework and lab assignments, and meet to answer design or class related questions. There will be 3 (announced) quizzes in addition to the project. Design planning must include a test plan and ensure that members of the team will be present in the fall to test the fabricated designs and that such testing will be practical. Design teams are strongly encouraged to include members with differing backgrounds to cover the design requirements.
Note-- lecture notes are provided here for early perusal. The course is moving to support mixed signal/analog issues as well as digital ones so the notes are likely to change over the quarter. I will indicate the lectures that have been updated.
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Last Updated: March 27, 2011