University of California, Santa
Department of Electrical and Computer Engineering
VLSI Project Design
ECE 224A - Spring 2014
Instructor: Prof. Forrest Brewer 729-1410
Schedule:Mon/Wed 10-11:50 Phelps 1160
The course curricula and tools now support mixed signal design practice as well as conventional digital design. Projects may be either digital, mixed or analog as desired. The tools will include Cadence Virtuoso and Silicon Encounter as well as Synopsys Design Compiler for Verilog based design. We will also support full custom, array and data path tools from MMI. Most designs will use the On-Semi 0.6um C5 process through vendor specific rules allowing 3-metal, 2-poly technology with several resistor and capacitor types including isolated poly/poly caps with 10% typical variance. The rules also support NPN bipolar transistors, varactors and Schottky diodes. The vendor rules also support a rich standard cell set and a newly designed 48-pin (max) pad=frame with up to 2500 standard cells in the 2.25mm^2 design space. Since the design area is relatively small for this level of integration, projects will have limited external signaling capacity, and are encouraged to integrate sensors such as photo-diodes, Hall-effect devices, or mixed-signal designs in lieu of pure digital constructions.
You need not fabricate a design to receive full credit in the class, but you do need to bring your design to the level that it can be fabricated before grades are assigned. In particular, this means full Verilog simulation of the digital parts, full-chip DRC and LVS including metal density and contact reliability rules and full-chip extraction and power-up simulation at the pad level to ensure things are as functional as you can make them. Fabrication comes with the proviso that you will provide testing when the chips are returned from fabrication. This means that at least one member of your group must be attending in the fall or winter quarter to test the designs.
There is a portable linux version of the MMI tool set available for personal computer use in this course so that design and analysis work need not be completed in the ECI lab. If interested, please see me about this.
This course stresses practical layout and full/semi-custom design techniques leading to fabrication of VLSI integrated circuits. Given the short design time, a structured methodology will be used stressing design modeling and constraint based design. The projects will be completed by small groups (2-3people) and must meet design goals including area, performance, validation, test and manufacturability to complete the course. These constraints ensure that the final design can be fabricated and that every measure has been taken to ensure a working design.
Course Organization: Lectures M,W 10-12, periodic homework and lab assignments, and meet to answer design or class related questions. There will be 3 (announced) quizzes in addition to the project. Design planning must include a test plan and ensure that members of the team will be present in the fall to test the fabricated designs and that such testing will be practical. Design teams are strongly encouraged to include members with differing backgrounds to cover the design requirements.
There is a very simple way to improve your grade in this class and it will pay off for years. Instead of going to class as the usual pattern and discovering what you don't know for later study, try reading the lecture material (either text book or notes) in advance on the day before the lecture. The idea is to build a scaffold of information in your own mind and with your personal referents (i.e. what you already know). During lecture, take notes anyway, in your own words and try to keep a self-consistent picture of the ideas and applications. It is perfectly appropriate to briefly follow side routes to make sure of your understanding. The major benefit is that you can ask questions when confused – you are not overloaded with notes as you've seen it before and your questions stem from deeper issues than simple misunderstanding. The upshot is that you are active during lecture, not asleep which is much more common. Homework is then a test of your understanding of the material. The key benefit is that you are actively involved in translating the information into your own thought patterns, i.e. you make it yours. Another benefit is that you will find you do not need to cram for the exam since you already reviewed it twice. As a last note, keep your notes – 6 months or so later, review them to 'set' the key ideas of the class. Studies indicate that typical students lose 85% of the information they gain in a class in the next year. They also show that the review above roughly doubles what you retain. This effectively makes your twice as 'smart'. You have more and deeper insights and you also have much more time in the crunch periods since you don't need to 'cram', a technique that works so poorly it is amazing how common it is.
Digital Integrated Circuits- Rabaey et. all 2nd ed. Prentice-Hall (fair overview of logic some memory)
Weste (4th) (Good all round intorduction, cleaned up logical effort (Harris))
Analog Layout- Hastings, 2nd ed. Prentice-Hall (essential starter for analog layout)
"Digital VLSI Chip Design wih Candence and Synopsys CAD Tools", Brunvand (overview of logic design featuring Verilog/VHDL and standard cell tools)
Note-- lecture notes are provided here for early perusal. The course is moving to support mixed signal/analog issues as well as digital ones so the notes are likely to change over the quarter. I will indicate the lectures that have been updated. (Some course information is only available on Gauchospace).
Lecture #1 Notes (update) -powerpoint
Lecture #2 Notes (update) -powerpoint
Lecture #4 Notes - powerpoint
Lecture #5 Notes - powerpoint
Lecture #6 Notes - powerpoint
Lecture #7 Notes - powerpoint
Lecture #8 Notes - powerpoint
Lecture #8a Notes - powerpoint
Lecture #9 Notes - powerpoint
Lecture #a (G. Anelli/CERN) - powerpoint
Lecture #b (G. Anelli/CERN) - powerpoint
Lecture #10 Notes - powerpoint
Lecture #12b Notes powerpoint
Last Updated: March 27, 2011