MOSIS Layer Map for SCN3ME and SCN3ME_SUBM

This is the layer map for the technology codes SCN3ME and SCN3ME_SUBM using the MOSIS Scalable CMOS layout rules (SCMOS), and only for SCN3ME and SCN3ME_SUBM. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCN3ME: Scalable CMOS N-well, 3 metal, non-silicided, high resistance layer available. Adds a second polysilicon layer (poly2) as the upper electrode of a poly capacitor.

SCN3ME_SUBM: Uses revised layout rules for better fit to sub-micron processes (see MOSIS Scalable CMOS (SCMOS) Design Rules, section 2.4).

Fabricated on AMI 0.50 micron process runs.