SCMOS Layout Rules - Poly2 for Capacitor

The poly2 layer is a second polysilicon layer (physically above the standard, or first, poly layer). The oxide between the two polys is the capacitor dielectric. The capacitor area is the area of coincident poly and electrode.


Rule Description Lambda
SCMOS SUBM DEEP
11.1 Minimum width 3 7 n/a
11.2 Minimum spacing 3 3 n/a
11.3 Minimum poly overlap 2 5 n/a
11.4 Minimum spacing to active or well edge
(not illustrated)
2 2 n/a
11.5 Minimum spacing to poly contact 3 6 n/a
11.6 Minimum spacing to unrelated metal 2 2 n/a

 


SCMOS Layout Rules - Poly2 for Transistor
Same poly2 layer as for caps



Rule Description Lambda
SCMOS SUBM DEEP
12.1 Minimum width 2 2 n/a
12.2 Minimum spacing 3 3 n/a
12.3 Minimum electrode gate overlap of active 2 2 n/a
12.4 Minimum spacing to active 1 1 n/a
12.5 Minimum spacing or overlap of poly 2 2 n/a
12.6 Minimum spacing to poly or active contact 3 3 n/a
 


SCMOS Layout Rules - Poly2 Contact


The poly2 is contacted through the standard contact layer, similar to the first poly. The overlap numbers are larger, however.

Contacts must be drawn orthogonal to the grid of the layout. Non-Manhattan contacts are not allowed.


Rule Description Lambda
SCMOS SUBM DEEP
13.1 Exact contact size 2 x 2 2 x 2 n/a
13.2 Minimum contact spacing 2 3 n/a
13.3 Minimum electrode overlap (on capacitor) 3 3 n/a
13.4 Minimum electrode overlap (not on capacitor) 2 2 n/a
13.5 Minimum spacing to poly or active 3 3 n/a