Ph.D., Electrical & Computer Engineering, University of California, Santa Barbara (2000)Areas of Expertise:
M.S., Electrical & Computer Engineering, University of California, Santa Barbara (1997)
B.S., Pacific Union College, Angwin (1991)
Computer Engineering: System-Level Computer-Aided Design, High-Level Synthesis, Design Automation, Scheduling, Symbolic Techniques, Reduced Ordered Binary Decision Diagrams, Automata Models, FPGAs, Computer Architecture, VLSI Design, Digital System DesignProfessional Engineering Experience:
Languages: C++, C, Python, Verilog, VHDL, Assembly, Tcl/tk, HTML, BASIC, FORTRAN
Operating Systems: UNIX (Linux and Solaris), DOS, Windows (3.1/95/98/NT/2000)
Senior CAD Engineer, Intel (2001- ):Professional Teaching Experience:
Applied research in high-level VLSI design and design automation
Freelance Designer (1998- ):
Designed, prototyped and tested FPGA-based PCI cards, Verilog IP cores, drivers and software libraries for niche applications
Graduate Student Researcher (1998-2000):
Created automata-based symbolic scheduling
Research Intern, Intel (1999):
Successfully applied Ph.D. research in symbolic scheduling to large industrial design problems
Design Intern, National Semiconductor (1997):
Implemented virtual mode for an embedded x86 processor
Contributed code to and helped debug a 50,000+ line C design model and Tcl/tk GUI
Fischer Computer Systems Intern/Engineer (1989-1993):
Performed quality control, repair and design of digital electronics products
Contract Teacher for Technical Research Associates, Inc. (1998-2000):Publications:
Developed and taught intensive course in Visual C++
Teaching Assistant at University of California, Santa Barbara (1995-1999):
Held responsible for laboratory sections, laboratory renovation, periodic lectures, office hours and grading
Teacher at San Fernando Valley Academy, Northridge (1993-1995):
Taught computer literacy, physics, chemistry, earth science, biology and math
S. Haynal, Automata-Based Symbolic Scheduling, Ph.D. Dissertation, University of California, Santa Barbara, 2000.Honors:
S. Haynal and F. Brewer, "Automata-Based Symbolic Scheduling for Looping DFGs", IEEE Trans. on Computers, to appear, 2000.
S. Haynal and F. Brewer, "Representing and Scheduling Looping Behavior Symbolically", Proc. IEEE Int. Conf. Computer Design, pp. 552-555, 2000.
S. Haynal and F. Brewer, "A Model for Scheduling Protocol-Constrained Components and Environments", Proc. of 36th ACM/IEEE Design Automation Conf., pp. 292-295, 1999.
S. Haynal and F. Brewer, "Efficient Encoding for Exact Symbolic Automata-Based Scheduling", IEEE Int. Conf. Computer-Aided Design, pp. 477-481, 1998.
S. Haynal and B. Parhami, "Arithmetic Structures for Inner-Product and Other Computations Based on a Latency-Free Bit-Serial Multiplier Design", Proc. of the 30th Asilomar Conf. on Signals, Systems, and Computers, pp. 197-201, 1996.
Awarded Delco Defense Systems Operations Graduate Fellowship (1998)References: Available on request.
Won second place, experienced category, in University of Michigan's VLSI design contest for the Rogue data compress-encrypt chip (Slides, Contest Paper) (1997)
Awarded Teacher of the Year at San Fernando Valley Academy (1995)
Received Richard E. Fischer Award for excellence in technology (1990)
Won California Resource Conservation Software Competition (1983)