MOSIS Layer Map for SCN3M and SCN3M_SUBM

This is the layer map for the technology codes SCN3M and SCN3M_SUBM using the MOSIS Scalable CMOS layout rules (SCMOS), and only for SCN3M and SCN3M_SUBM. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCN3M: Scalable CMOS N-well, 3 metal, 1 poly with silicide block option available only on the Agilent/HP process.

SCN3M_SUBM: Uses revised layout rules for better fit to sub-micron processes (see section 2.4)

Fabricated on either Agilent/HP or AMI 0.50 micron process runs. See "Notes" section of layer map for foundry-specific options.