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This is the layer map for the technology code SCNPC using the MOSIS Scalable CMOS layout rules (SCMOS), and only for SCNPC. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.
SCNPC: Scalable CMOS N_well 2 metal, 1 poly process with a layer for linear capacitors.
Fabricated on AMI 0.80 micron process runs.
Layer GDS CIF CIF Synonym Rule
SectionNotes N_WELL 42 CWN 1 ACTIVE 43 CAA 2
POLY_CAP1 28 CPC 23 Optional POLY 46 CPG 3
N_PLUS_SELECT 45 CSN 4
P_PLUS_SELECT 44 CSP 4
CONTACT 25 CCC CCG 5, 6, POLY_CONTACT 47 CCP 5 Can be replaced by CONTACT ACTIVE_CONTACT 48 CCA 6 Can be replaced by CONTACT METAL1 49 CM1 CMF 7
VIA 50 CV1 CVA 8
METAL2 51 CM2 CMS 9
GLASS 52 COG 10
PADS 26 XP
Non-fab layer used to highlight pads Comments -- CX Comments