XPIC Microcontroller Design

Scott Masch, Forrest Brewer


This is a superset design of the popular Microchip PIC 14-bit instruction microcontrollers. It is implemented in 0.5um HP (HP14TB) technology
and achieves 100MHz operation at 1 instruction per clock at 3.3V. The design is written in FML (Synopsys Protocol Compiler) which is technolgy
related to the PBS synthesis system research. The actual design document for the fully optimized design is 11 pages of FML, of which a majority
is macro definitions. The design was undertaken to explore the feasibility of Microprocessor design using Extended regular languages which have
substantial benefit for both verification and for ease of specification and quality of the constructed fsm's.


The XPIC (Master's Thesis, December 2001) - This is the final report on the XPIC. This document includes everything from the User's Manual to how the design was specified using FML. Also includes information on testing as well as the FML source and the source code for the ROM.

Design Test Document (November 2001) - This is an early version of "The XPIC" (above) that was geared primarily as a test report. It includes a description of what the XPIC is. Unless you are only interested in the testing, you probably don't want this: instead, get "The XPIC", above.

Xpic GDS2, layer map, verilog and verilog testbench. Note the xpic design is copyright 2001 by Scott Masch, Forrest Brewer and UCSB.