* FILE: lab6.sp

********************** begin header *****************************

* Sample Header file for Generic 1.8V 0.18um process (g18)

.OPTIONS post ACCT OPTS lvltim=2 NOMOD

.param  arean(w,sdd) = '(w*sdd*1p)'
.param  areap(w,sdd) = '(w*sdd*1p)'
* Setup either one or the other of the following
* For ACM=0,2,10,12 fet models
.param  perin(w,sdd) = '(2u*(w+sdd))'
.param  perip(w,sdd) = '(2u*(w+sdd))'
* For ACM=3,13 fet models
*.param  perin(w,sdd) = '(1u*(w+2*sdd))'
*.param  perip(w,sdd) = '(1u*(w+2*sdd))'

.param ln_min   =  0.18u
.param lp_min   =  0.18u

* used in source/drain area/perimeter calculation
.param sdd        =  0.43

.PARAM vddp=1.8		$ VDD voltage

VDD vdd 0 DC vddp 

.TEMP 70
.TRAN 50p 1u
*********************** end header ******************************

* SPICE netlist for "lab6" generated by MMI_SUE5.1.9 on Tue Feb 26 
*+ 10:48:09 PM PST 2008.

* start main CELL lab6
* .SUBCKT lab6 vgnd vvdd 
R_1 net_12 net_5 0.1 
C_1 gnd net_12 100u 
C_2 gnd net_4 0.9n 
C_3 net_7 net_6 0.9n 
L_1 net_6 net_4 60p 
L_2 gnd net_7 60p 
C_4 net_10 net_2 160p 
R_2 net_8 net_10 10m 
R_3 net_9 net_6 1m 
R_4 net_7 net_1 1m 
L_3 net_5 vdd 0.1u 
L_4 net_4 net_5 0.17u 
Ilogic vvdd vgnd PWL(0 0 2.55n 0 2.65n 60 2.75n 60 2.95n 0) R 
C_5 gnd net_11 4500u 
L_5 net_11 net_3 1.67n 
R_5 net_3 net_4 0.0167 
Ipins vvdd vgnd PWL(0 0 9.85n 0 10.15n 8 11.85n 8 12.15n 0 14.85n 0 
+ 15.15n 8 19.85n 8 20.15n 0) R 
C_6 net_1 net_9 C1 
C_7 vgnd vvdd C2 
R_6 vvdd net_2 2m 
R_7 net_8 vgnd 2m 
L_6 net_2 net_9 50p 
L_7 net_1 net_8 50p 
* .ENDS	$ lab6

.GLOBAL gnd vdd

.END